Simple Nios II on the DE0-Nano - Part 2 of 4 (Qsys)

It first post in this series I designed on the architecture for a simple Nios II system. I also did some preliminary steps to create a project we and use as a platform to for our system.

QSYS

Qsys is the tool for designing our processor hardware. It allow the different blocks of the system to be connected together and configured. The following steps will take you through the steps in creating our system.

The first component I added was the RAM configured to be 20Kbytes. No a huge amount of memory but more than enough to write a simple program to flash some LED's. 

Next I added the processor. I used the economic version of the Nios because this will work with the web edition of the software without any additional licenses. Note you can only set the reset and exception vectors once it has been connected to the RAM.

The JTAG uart  will allow us to download our software from the PC into the RAM.

The System ID is used to match the hardware and the software. You should never build any Nios system without a System ID component include. 

The PIO is configured for output only and will be used for driving the Led's.

Now all the components are included in the design we need to make sure all the blocks are connect correctly.

Once we have finished building the system you can look in the HDL tab and get the details of how to include a component. We will use this in the next posts when we include our QSYS component into our FPGA design.

We have now come to the end of our QSYS section. The only thing left to do is generate our QSYS system. I have called mine my_nios1. 

In my next post we will see how we take this QSYS model and include into some hardware using VHDL!

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Simple Nios II on the DE0-Nano - Part 1 of 4 (Project creation)

Simple Nios II on the DE0-Nano - Part 2 of 4 (Qsys)

Simple Nios II on the DE0-Nano - Part 3 of 4 (VHDL)

Simple Nios II on the DE0-Nano - Part 4 of 4 (Nios Software)