Using a PLL to correct the SDRAM clock when using a Nios II on the DE0-Nano

In my previous blog post Connecting the SDRAM to a Nios II on the DE0-Nano I wrote about my experiences of connecting up the 32MByte SDRAM chip to the Nios processor. Hooray it all worked as expected.

But is there an issue in the design that is waiting to cause me trouble! The clock skew depends on the physical characteristics of the DE0-Nano board [2]. The sdram_clock needs to lead the system clock in the design by 3 nanosecond. This can be done using a PLL or Phased-Locked-Loop.

Phased-Locked-Loop

A Phase-Locked-Loop or PLL is a control system that will produce an output signal that is related to the phase of the input signal. They can be used to increase or decrease the clock frequency. They can more importantly in our case allow us to produce another clock that has the same frequency as the source but is out of phase by a fixed amount. The Cyclone IV E used on the DE0-Nano has a general purpose PLL that can be used of extending memory interfaces and is ideal for what we want to do.

Adding a PLL

The MegaWizard plugin manager can be used to generate and configure our PLL.

When the megawizrd start we need to first select the correct PLL component called ALTPLL and give it a name. I have called mine sdram_pll.

The input frequency feeding the PLL is 50Mhz.

I removed the signal telling me when the PLL what frequency and phase lock. I am not worried about that in this design.

Finally I configure the output frequency of the PLL to be the same as the input frequency but with a phase shift of -3ns. That's all I need to generate and configure my PLL. All I need to do now is stitch the PLL into my design.

VHDL

To the architecture in my previous post I added the following component deceleration for the PLL:

component sdram_pll is

PORT

(

areset : IN STD_LOGIC := '0';

inclk0 : IN STD_LOGIC := '0';

c0 : OUT STD_LOGIC

);

end component;

I also needed to add a signal for the rest because the PLL reset is active high and the Nios II reset is active low!

signal reset: std_logic;

Not we have the component we can connect it into our VHDL architecture.

--pin_sdram_clk <= pin_clk;

reset <= not pin_reset_n;

sdram_pll_inst : sdram_pll port map

(

areset => reset,

inclk0 => pin_clk,

c0 => pin_sdram_clk

);

You can see I have just comment out the existing line that connects the sdram_clk with the system clock and replaced with the PLL component. Notice written the logic to invert the the reset input because the reset is active high. I have taken the reset directly from the reset pin. This is something I do not like doing an in my next post I will address this issue. However for now it is done and it works.