For Loop for driving a testbench

Building again on my blog post Reporting on Std_Logic_Vector I wanted to build on the VHDL to split the constant out into a number of signal that I could use as part of a test bench. Before I look at how the test bench could be constructed the following VHDL will split out the signals a,b,c and z_expected: 


library ieee;
use ieee.std_logic_1164.all;

entity testxx is
end entity;

architecture arch of testxx is

--The function to_string was taken from 
--http://www-ee.uta.edu/Online/Zhu/spring_2007/tutorial/how_to_print_objexts.txt
  function to_string(sv: Std_Logic_Vector) return string is
    use Std.TextIO.all;
    variable bv: bit_vector(sv'range) := to_bitvector(sv);
    variable lp: line;
  begin
    write(lp, bv);
    return lp.all;
  end;
  
  type tvector is array (7 downto 0) 
              of std_logic_vector(3 downto 0);

  constant test_vectors: tvector := ("0000", 
                                     "0011", 
                                     "0101", 
                                     "0111", 
                                     "1001", 
                                     "1010", 
                                     "1100",
                                     "1111");

  signal a,b,c,z_expected: std_logic;
  
  begin
  
  process
    begin
       for i in 7 downto 0 loop
        report "loop_i=" & integer'image(i);
        report "length=" 
               & integer'image(test_vectors(i)'length);
        report "vector=" & to_string(test_vectors(i));
        
        a <= test_vectors(i)(3);
        b <= test_vectors(i)(2);
        c <= test_vectors(i)(1);
        z_expected <= test_vectors(i)(0);
        
        wait for 10 ns;
       end loop;
      wait;
  end process;
  
  process(a)
    begin 
      report "----a has changed to: " & Std_Logic'image(a);
  end process;
  
  process(b)
    begin 
      report "----b has changed to: " & Std_Logic'image(b);
  end process;
  
  process(c)
    begin 
      report "----c has changed to: " & Std_Logic'image(c);
  end process;
  
  process(z_expected)
    begin 
      report "----z_expected has changed to: " & Std_Logic'image(z_expected);
  end process;
end architecture;

The output from modelsim is a follows:


Note: ----z_expected has changed to: 'U'
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: ----c has changed to: 'U'
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: ----b has changed to: 'U'
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: ----a has changed to: 'U'
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: loop_i=7
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: vector=0000
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: ----a has changed to: '0'
#    Time: 0 ps  Iteration: 1  Instance: /testxx
# ** Note: ----b has changed to: '0'
#    Time: 0 ps  Iteration: 1  Instance: /testxx
# ** Note: ----c has changed to: '0'
#    Time: 0 ps  Iteration: 1  Instance: /testxx
# ** Note: ----z_expected has changed to: '0'
#    Time: 0 ps  Iteration: 1  Instance: /testxx
# ** Note: loop_i=6
#    Time: 10 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 10 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=0011
#    Time: 10 ns  Iteration: 0  Instance: /testxx
# ** Note: ----c has changed to: '1'
#    Time: 10 ns  Iteration: 1  Instance: /testxx
# ** Note: ----z_expected has changed to: '1'
#    Time: 10 ns  Iteration: 1  Instance: /testxx
# ** Note: loop_i=5
#    Time: 20 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 20 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=0101
#    Time: 20 ns  Iteration: 0  Instance: /testxx
# ** Note: ----b has changed to: '1'
#    Time: 20 ns  Iteration: 1  Instance: /testxx
# ** Note: ----c has changed to: '0'
#    Time: 20 ns  Iteration: 1  Instance: /testxx
# ** Note: loop_i=4
#    Time: 30 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 30 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=0111
#    Time: 30 ns  Iteration: 0  Instance: /testxx
# ** Note: ----c has changed to: '1'
#    Time: 30 ns  Iteration: 1  Instance: /testxx
# ** Note: loop_i=3
#    Time: 40 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 40 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=1001
#    Time: 40 ns  Iteration: 0  Instance: /testxx
# ** Note: ----a has changed to: '1'
#    Time: 40 ns  Iteration: 1  Instance: /testxx
# ** Note: ----b has changed to: '0'
#    Time: 40 ns  Iteration: 1  Instance: /testxx
# ** Note: ----c has changed to: '0'
#    Time: 40 ns  Iteration: 1  Instance: /testxx
# ** Note: loop_i=2
#    Time: 50 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 50 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=1010
#    Time: 50 ns  Iteration: 0  Instance: /testxx
# ** Note: ----c has changed to: '1'
#    Time: 50 ns  Iteration: 1  Instance: /testxx
# ** Note: ----z_expected has changed to: '0'
#    Time: 50 ns  Iteration: 1  Instance: /testxx
# ** Note: loop_i=1
#    Time: 60 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 60 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=1100
#    Time: 60 ns  Iteration: 0  Instance: /testxx
# ** Note: ----b has changed to: '1'
#    Time: 60 ns  Iteration: 1  Instance: /testxx
# ** Note: ----c has changed to: '0'
#    Time: 60 ns  Iteration: 1  Instance: /testxx
# ** Note: loop_i=0
#    Time: 70 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 70 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=1111
#    Time: 70 ns  Iteration: 0  Instance: /testxx
# ** Note: ----c has changed to: '1'
#    Time: 70 ns  Iteration: 1  Instance: /testxx
# ** Note: ----z_expected has changed to: '1'
#    Time: 70 ns  Iteration: 1  Instance: /testxx